Science and Technology Daily (Reporter Zhang Jiaxin) – Low-dropout linear regulators (LDOs) are the "voltage regulation heart" inside chips, providing clean and stable power to various functional modules. A research team at the Ulsan National Institute of Science and Technology in South Korea has developed an ultra-miniature hybrid LDO that promises to significantly improve the power management efficiency of advanced semiconductor devices. It not only provides a more stable output voltage but also filters out noise while occupying less space, offering a new solution for high-performance systems-on-chips in fields such as artificial intelligence and 6G communications. The relevant findings were published in the latest issue of the IEEE SolidState Circuits journal.

The new LDO employs a hybrid design that integrates analog and digital circuitry, combining the advantages of both to ensure a stable voltage supply even when current demands fluctuate dramatically. For example, it ensures a stable power delivery when a smartphone is playing a demanding game, effectively preventing unwanted noise from the power supply.

What makes this research unique is its use of advanced digital-to-analog conversion methods and local grounding generator technology. These two technologies work together to achieve superior voltage stability and noise suppression. Experimental data shows that even with rapid current fluctuations of up to 99 mA, the chip voltage ripple is only 54 mV, and it can recover to normal voltage within 667 nanoseconds. Furthermore, at a frequency of 10 kHz and a load of 100 mA, the power supply rejection ratio reaches -53.7 dB, almost completely filtering out power supply noise within that frequency range.

Another major advantage of the new LDO is its size. It requires no external capacitors, is manufactured using a 28nm CMOS process, and has a chip area of ​​only 0.032 square millimeters, significantly saving space. The team states that traditional hybrid LDOs often rely on large capacitors to smooth the digital-to-analog conversion, which limits their application in high-density on-chip systems. The new design, through a seamless digital-to-analog conversion process, both reduces size and improves energy efficiency.

The new LDO also features extremely low standby power consumption, activating only during bursts of power demand, further enhancing system energy efficiency. Its overall performance index is only 0.029 picoseconds, setting a new record.